Method for adding an implant at the shallow trench isolation corner in a semiconductor substrate

ABSTRACT

A method for fabricating corner implants in the shallow trench isolation regions of an image sensor includes the steps of forming a photoresist layer on a first hard mask layer overlying an etch-stop layer on a semiconductor substrate. The photoresist mask is patterned to create an opening and the portion of the first hard mask layer exposed in the opening is etched down to the etch-stop layer. A first dopant is implanted into the semiconductor substrate through the exposed etch-stop layer. The photoresist mask is removed and a second hard mask layer is formed on the remaining structure and etched to create sidewall spacers along the side edges of the first hard mask layer. The etch stop layer and the semiconductor substrate positioned between the sidewall spacers are etched to create a trench and a second dopant implanted into the side and bottom walls of the trench.

CROSS-REFERENCE TO RELATED APPLICATIONS

Reference is made to and priority claimed from U.S. ProvisionalApplication Ser. No. 60/842,075, filed Sep. 1, 2006 entitled METHOD FORADDING AN IMPLANT AT THE SHALLOW TRENCH ISOLATION CORNER.

TECHNICAL FIELD

The present invention generally relates to a method of fabricating anintegrated circuit in a semiconductor device. More particularly, thepresent invention relates to fabricating an implant at the shallowtrench isolation corner of an image sensor to suppress the surface darkcurrent.

BACKGROUND

Typically metallic or lattice defects, surface states, and latticestress produce dark current in image sensors. Dark current is anundesirable signal that is generated in a semiconductor substrate andcollected by a photodetector. Dark current is generated when light isboth striking and not striking the photodetector. Dark current addsnoise, which reduces the dynamic range and the signal-to-noise ratio ofthe image sensor.

Shallow trench isolation physically isolates pixels so that signalcollected in any given pixel will not spill over to the neighboringpixel or pixels. Unfortunately, STI features can potentially producesurface dark current because the features create additional surfacestates and localized high stress regions. Image sensors, such asComplementary Metal Oxide Semiconductor (CMOS) image sensors, with STIregions suffer from high surface dark current at the sidewalls andbottom of the STI trench. Typically, high angle implants are performedon the sides and bottom of the STI regions to reduce the surface darkcurrent. Additionally, corner implants further suppress surface darkcurrent.

FIG. 1 shows a cross-sectional view of a semiconductor substrate with ashallow trench isolation region according to the prior art. Substrate 10includes a STI having a trench with corner implants 13 and sidewallimplants 14. One conventional method for fabricating corner implants 13requires the formation and patterning of photoresist mask 12 on thedevice and the implantation of dopants (represented by arrows) into thecorners of the shallow trench. Unfortunately, the formation andpatterning of photoresist mask 12 creates an additional processing stepin the manufacture of semiconductor devices.

Another method to form corner implants 13 is to remove a hard mask (notshown) from the sidewalls and corners of the shallow trench region ofthe semiconductor substrate and then simultaneously implant both thesidewalls and corners. Unfortunately, subsequent etches performed duringthe fabrication process can create undesirable silicon pits at thecorner implants of the STI.

Therefore, there exists a need in image sensors to reduce the surfacedark current in the sidewall implant.

Furthermore, there exists a need to provide a method for forming ashallow trench isolation that is self-aligned.

Additionally, there exists a need for forming corner implants that doesnot create silicon pits in the STI corner during subsequent processingof the image sensor.

SUMMARY

The present invention is directed to overcoming one or more of theproblems set forth above. The present invention relates to a method forfabricating an image sensor with corner implants in the shallow trenchisolation regions. The method includes the steps of forming a first hardmask layer of over an etch-stop layer on a semiconductor substrate andproviding a photoresist mask over the hard mask layer. The photoresistmask is patterned to create an opening and the portion of the first hardmask layer exposed in the opening is etched down to the etch-stop layer.A first dopant is then implanted into the semiconductor substratethrough the exposed etch-stop layer. The photoresist mask is removed anda second hard mask layer is formed on the remaining structure and etchedto create sidewall spacers along the side edges of the first hard masklayer. The etch stop layer and the semiconductor substrate positionedbetween the sidewall spacers are then etched to create a trench and asecond dopant implanted into the side and bottom walls of the trench.The trench is then typically filled with a dielectric material to createa shallow trench isolation region in the semiconductor substrate.

The present advantage has the advantage of reducing the surface darkcurrent by forming corner implants that do not cause silicon pittingwith a shallow trench isolation that is self-aligned.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features, and advantages of the presentinvention will become more apparent when taken in conjunction with thefollowing description and drawings wherein identical reference numeralshave been used, where possible, to designate identical features that arecommon to the figures, and wherein:

FIG. 1 shows a cross-sectional view of a semiconductor substrate with ashallow trench isolation region according to the prior art;

FIG. 2 shows a cross-sectional view of a semiconductor substrate and afirst hard mask layer in an embodiment in accordance with the invention;

FIG. 3 shows a cross-sectional view of a semiconductor substrate with anetched first hard mask layer in an embodiment in accordance with theinvention;

FIG. 4 shows a cross-sectional view of a semiconductor substrate with ashallow implant in an embodiment in accordance with the invention;

FIG. 5 shows a cross-sectional view of a semiconductor substrate with asecond hard mask layer in an embodiment in accordance with theinvention;

FIG. 6 shows a cross-sectional view of a semiconductor substrate with anetched second hard mask layer in an embodiment in accordance with theinvention;

FIG. 7 shows a cross-sectional view of a semiconductor substrate with ashallow trench in an embodiment in accordance with the invention;

FIG. 8 shows a cross-sectional view of a semiconductor substrate with ashallow trench isolation and side wall implants in an embodiment inaccordance with the invention;

FIG. 9 a shows a first cross-sectional view of a semiconductor substratecontaining devices between two shallow trench isolations with sidewallimplants in embodiments in accordance with the invention; and

FIG. 9 b shows a second cross-sectional view of a semiconductorsubstrate containing devices between two shallow trench isolations withsidewall implants in embodiments in accordance with the invention.

DETAILED DESCRIPTION

The present invention includes a method for forming corner implants inSTI regions of an integrated circuit. The implant is self-aligned to theSTI corner without the need for additional photoresist masking orexposing the STI corner, which can lead to silicon pitting. The presentinvention is described with reference to the accompanying drawings, inwhich exemplary embodiments of the invention are shown. The inventionmay, however, be embodied in may different forms and should not beconstrued as being limited to the embodiments set forth herein; rather,these embodiments are provided to fully convey the concept of thepresent invention to those skilled in the art. The drawings are not toscale and many portions are exaggerated for clarity.

Referring to FIG. 2, a cross-sectional view of a semiconductor substrateand a first hard mask layer in an embodiment in accordance with theinvention is shown. Semiconductor substrate 20 is silicon, siliconcarbide, silicon-on-insulator, silicon-germanium, gallium-nitride, orgallium-arsenide in one embodiment in accordance with the invention.Furthermore, semiconductor substrate 20 can be n-type, p-type or anundoped substrate. Additionally, semiconductor substrate 20 mayoptionally have an epitaxial layer (not shown) that is the same oropposite conductivity type as semiconductor substrate 20. Semiconductorsubstrate 20 may also contain wells that are of the same or oppositeconductivity type as either the epitaxial layer or semiconductorsubstrate 20 implanted therein.

Etch-stop layer 21 is formed on the surface of semiconductor substrate20. In one embodiment in accordance with the invention, etch-stop layer21 is formed as a thin layer of silicon dioxide or polysilicon. Asilicon dioxide etch-stop layer may be grown on the substrate in oxygenor steam typically at 800-1200° C. Alternatively, etch stop layer 21 maybe deposited directly on the surface of semiconductor substrate 20 byoxide chemical vapor deposition. Oxide chemical vapor deposition isaccomplished by a low-pressure low temperature deposition or a plasmaenhanced chemical vapor deposition.

First hard mask layer 22 is deposited on etch-stop layer 21 viatraditional processes such as low pressure chemical vapor deposition(LPCVD) or plasma enhanced chemical vapor deposition (PECVD). First hardmask layer 22 is configured as any mask layer that is deposited or grownon the device. Examples of a hard mask layer include, but are notlimited to, silicon nitride, polysilicon and a metal film.

FIG. 3 shows a cross-sectional view of a semiconductor substrate with anetched first hard mask layer in an embodiment in accordance with theinvention. Photoresist mask 23 is coated onto first hard mask layer 22and patterned to form opening 18. An anisotropic etch is then performedto remove the portion of first hard mask layer 22 exposed in opening 18.Opening 19 in first hard mask layer 22 is wider than the width of ashallow trench that will be formed in semiconductor substrate 20.

Referring to FIG. 4, a cross-sectional view of a semiconductor substratewith a shallow implant in an embodiment in accordance with the inventionis shown. Shallow implant 24 is typically implanted to a depth between100 and 500 A in an embodiment in accordance with the invention.Photoresist mask 23 and first hard mask layer 22 serve as a protectivemask for the regions of the semiconductor substrate in which a shallowimplant is not to be formed. Shallow implant 24 is a dopant having aconductivity type opposite the conductivity type of the photodetectors(not shown) in the image sensor. In one embodiment in accordance withthe invention, the dopant is an n-type dopant such as phosphorus,arsenic, or antimony. In another embodiment in accordance with theinvention, the dopant is a p-type dopant such as boron, aluminum,gallium or indium.

The implant energy depends on the particular dopant used and istypically between 5-200 KeV for an implant depth typically between 100and 500 A. The implant profile distribution is such that the implantdopant remains near the surface of substrate 20. If thermal processingoccurs after implantation the dopant will diffuse away from the initialimplant area. This diffusion is accounted for when choosing the initialimplant depth and concentration of the elementary dopant.

Photoresist mask 23 is then removed by an oxygen ashing process, wetsulfuric acid mixed with peroxide, or solvent chemistry methods. Ifadequate thickness is used for first hard mask layer 22, photoresistmask 23 is removed and first hard mask layer 22 is the protective maskfor the implant in an embodiment in accordance with the invention. Inanother embodiment in accordance with the invention, shallow implant 24is formed in substrate 20 before first hard mask layer 22 isansiotropically etched.

FIG. 5 shows a cross-sectional view of a semiconductor substrate with asecond hard mask layer in an embodiment in accordance with theinvention. Second hard mask layer 25 is deposited on first hard masklayer 22 and the exposed portion of etch-stop layer 21. Second hard masklayer 25 may be of the same or different material than first hard masklayer 22. Second hard mask layer 25 is of a material that has a slowremoval rate during an STI anisotropic etch when compared to the siliconremoval rate in an embodiment in accordance with the invention.

Referring to FIG. 6, a cross-sectional view of a semiconductor substratewith an etched second hard mask layer in an embodiment in accordancewith the invention is shown. An anisotropic etch, such as plasmaetching, is used to form sidewall spacers 26 along the sides of firsthard mask layer 22. Sidewall spacers 26 are positioned over theperimeter portions of shallow implant 24. Sidewall spacers 26 eachtypically have a width between 0.05 and 0.2 μm in an embodiment inaccordance with the invention. The width of sidewall spacers 26 isprimarily controlled by the thickness of second hard mask layer 25 (seeFIG. 5).

FIG. 7 shows a cross-sectional view of a semiconductor substrate with ashallow trench in an embodiment in accordance with the invention.Shallow trench 40 is formed by anisotropically etching through shallowimplant 24 and into semiconductor substrate 20. Shallow trench 40 isformed in the area between sidewall spacers 26 in semiconductorsubstrate 20. Corner implants 27 are the only portions of shallowimplant 24 to remain in substrate 20. By etching through opening 19 insecond hard mask layer 25, the inside edges of corner implants 27 areself-aligned with the inside edge of second hard mask layer 25.

In one embodiment in accordance with the invention, shallow trench 40typically has a depth between 0.3 and 0.5 μm and a width between 0.15and 0.6 μm. The width of shallow trench 40 should be as small aspossible to minimize the amount of semiconductor substrate used for theSTI regions. Minimizing the size of the STI regions advantageouslyincreases the amount of substrate that is available for photodetectorsin an image sensor.

Referring to FIG. 8, the sidewalls and bottom of shallow trench 40 areimplanted with implant dopant 28. Implant dopant 28 is typicallyimplanted between 0 and 100 A from the exposed surface of the substrate20 and the concentration of implant dopant 28 is typically between10¹²-10¹³ atoms/cm² in an embodiment in accordance with the invention.This implant is usually done at an angle and quaded (i.e., done at fourseparate wafer rotations ninety degrees apart) so that implant dopant 28is implanted into all four sides and the bottom of shallow trench 40.

Implant dopant 28 is of the same conductivity type as the cornerimplants 27. In one embodiment in accordance with the invention, implantdopant 28 is also the same dopant as the shallow implant 24 dopant.Implant dopant 28 can be an n-type dopant such as phosphorus, arsenic,or antimony, or a p-type dopant such as boron, aluminum, gallium orindium.

Dielectric layer 29 is typically formed on the regions of the siliconimplanted with dopant 28 by a low-pressure chemical vapor deposition, anatmospheric pressure chemical vapor deposition, a plasma enhancedchemical vapor deposition, or a high density plasma deposition. Examplesof a dielectric material that can be used for dielectric layer 29include, but are not limited to, a liner oxide or nitride. Dielectriclayer 29 can be grown or deposited either prior to or after theimplantation of implant dopant 28. Isolation trench 40 is then filledwith a dielectric material (not shown).

Referring to FIG. 9 a, a first cross-sectional view of a semiconductorsubstrate containing devices between two shallow trench isolations withsidewall implants in embodiments in accordance with the invention isshown. STI regions 42, 43 are shown adjacent to photodetectors 30, 31,respectively. Photodetectors 30, 31 have a conductivity type that isopposite the conductivity type of implant dopant 28 and corner implants27. When transfer gate 32 is pulsed, charge is transferred from onephotodetector (e.g., photodetector 30) into floating diffusion 33, alsoreferred to as a sensing node, contained in well 34. The signal is thensensed by the pixel amplifier (not shown) and fed into the downstreamcircuitry (not shown) outside of the pixel array. Floating diffusion 33has a conductivity type that is opposite the conductivity type ofimplant dopant 28 and corner implants 27.

FIG. 9 b shows a second cross-sectional view of a semiconductorsubstrate containing devices between two shallow trench isolations withsidewall implants in embodiments in accordance with the invention. Theconductivity type of corner implants 27, implant dopant 28,photodetectors 30, 31, floating diffusion 33, well 34, and pining layers35, 36 is reversed with respect to the conductivity types shown in FIG.9 a.

The first hard mask layer and second hard mask layer have been removedfrom the structure shown in FIGS. 9 a and 9 b. However, it is understoodthat these layers may alternatively remain in the final structure.Although an image sensor with two shared photodetectors is shown inFIGS. 9 a and 9 b it is understood that any number of photodetectors maybe used. Typically one, two or four photodetectors can be connected to asingle floating diffusion by transfer gates. The photodetectors areusually formed at a depth that is less than the shallow trench.

PARTS LIST

10 semiconductor substrate 11 oxide film layer 12 photoresist mask 13corner implants 14 side wall implants 18 opening in photoresist mask 19opening in first hard mask layer 20 semiconductor substrate 21 etch-stoplayer 22 first hard mask layer 23 photoresist mask 24 shallow implant 25second hard mask layer 26 sidewall spacers 27 corner implants 28 implantdopant 29 dielectric layer 30 photodetector 31 photodetector 32 transfergate 33 floating diffusion 34 well 35 pining layer 36 pining layer 40shallow trench 42 shallow trench isolation 43 shallow trench isolation

1. A method for forming an isolation region in a semiconductor substrateto isolate devices formed in the substrate, comprising: forming ashallow implant in a portion of the semiconductor substrate byimplanting a first dopant through an opening in a first hard mask layer;forming a second hard mask layer over the portion of the semiconductorsubstrate and the first hard mask layer; etching the second hard masklayer to form sidewall spacers along the sides of the first hard masklayer, wherein each sidewall spacer overlies a portion of the shallowimplant in the semiconductor substrate; and etching into thesemiconductor substrate between the sidewall spacers to form anisolation trench.
 2. The method of claim 1, further comprising: formingan etch-stop layer over the semiconductor substrate surface; forming thefirst hard mask layer over the etch-stop layer; providing a photoresistmask layer over the first hard mask layer; patterning the photoresistmask layer to form an opening in the photoresist mask layer; and etchingthe first hard mask layer through the opening in the photoresist masklayer to form the opening in the first hard mask layer.
 3. The method ofclaim 1 further comprising: implanting a second dopant into the side andbottom walls of the isolation trench.
 4. The method of claim 3 furthercomprising forming a conformal insulating layer over the side and bottomwalls of the isolation trench.
 5. The method of claim 3 wherein thesecond dopant has the same conductivity type as the first dopant.
 6. Themethod of claim 2 further comprising the step of forming a photodetectorin the semiconductor substrate for capturing light and converting it toa charge, wherein the photodetector is laterally adjacent the isolationtrench.
 7. The method of claim 2 wherein the step of etching thesemiconductor substrate between the sidewall spacers to form anisolation trench self aligns the edge of the first dopant with the sidewalls of the hard mask layer.
 8. A method for forming a shallow trenchisolation region in an image sensor substrate to isolate devices formedin the substrate, comprising: a. forming an etch-stop layer on thesemiconductor substrate surface; b. forming a first hard mask layer overthe etch-stop layer, wherein the hard mask layer is comprised of amaterial that is different from a material in the etch-stop layer; c.providing a photoresist mask layer over the first hard mask layer; d.patterning the photoresist mask layer to form an opening in thephotoresist layer; e. etching the first hard mask layer through theopening in the photoresist mask layer to form an opening in the firsthard mask layer; f. implanting a first dopant through the opening in thephotoresist mask layer, through the opening in the first hard masklayer, and through the etch-stop layer to form a shallow implant in thesemiconductor substrate; g. removing the photoresist mask layer; h.forming a second hard mask layer over the structure remaining after stepg; i. etching the second hard mask layer to form sidewall spacers alongthe sides of the first hard mask layer, wherein each sidewall spaceroverlies a portion of the shallow implant in the semiconductorsubstrate; and j. etching through the etch-stop layer and into thesemiconductor substrate between the sidewall spacers to form anisolation trench.
 9. The method of claim 8, further comprisingimplanting a second dopant having the same conductivity type as thefirst dopant into the side and bottom walls of the isolation trench. 10.The method of claim 8 wherein said first dopant has a conductivity typethat is the same as the conductivity type of the underlying region inthe substrate.
 11. The method of claim 8 wherein said second hard masklayer is conformal.
 12. The method of claim 8 wherein etching the secondhard mask layer to form sidewall spacers on the sides of the first hardmask layer comprises anisotropically etching the second hard mask layerto form sidewall spacers on the sides of the first hard mask layer. 13.The method of claim 8 wherein etching through the etch stop layer andinto the semiconductor substrate between the sidewall spacers to form anisolation trench comprises anisotropically etching through the etch stoplayer and into the semiconductor substrate between the sidewall spacersto form an isolation trench.
 14. The method of claim 8 wherein saidsemiconductor substrate is selected from the group consisting ofsilicon, silicon-on-insulator, silicon-germanium and gallium-arsenide.15. The method of claim 8 further comprising the step of forming aconformal insulating layer over the side and bottom walls of theisolation trench prior to implanting the second dopant.
 16. The methodof claim 8 further comprising the step of forming a conformal insulatinglayer over the side and bottom walls of the isolation trench afterimplanting said second dopant.
 17. The method of claim 8 furthercomprising the step of forming a photodetector in the image sensorsubstrate for capturing light and converting it to a charge.